Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data in most areas of business, science, education and entertainment. These activities often involve storage of information. The manner in which the electronic devices perform storage operations can have a significant impact on performance and end results. However, traditional attempts at information storage have many limitations and can be very complex and complicated.
In modern microprocessors, the CPU execution core may speculatively execute memory LOAD instructions even through it is not known at the time of the speculative execution whether: (a) the LOAD instruction actually needs to be executed (as opposed to being the result of, e.g., a branch misprediction) and/or (b) the address used by the LOAD instruction has the architecturally correct value. The speculation can occur implicitly in hardware as a result of speculative execution in processors (e.g., related to out-of-order processing, in-order processing, pipeline processing, branch prediction processing, etc.), or it can be explicit in the software, through mechanisms such as the speculative loads of the Intel Itanium architecture (e.g., http://www.inntel.com/design/itanium/manuals/iiasdmanual.htm). In addition, prefetch operations (e.g., including pre-fetches inserted by semi-autonomous hardware engines such as stream-detections pre-fetchers, etc.) can be considered a form of speculative load.
Some traditional software code paradigms may include loading a value from memory conditional on some check. The aim of the check might be to guard against dereferencing illegal addresses. Due to speculation, however, the LOAD (corresponding to dereferencing the pointer) may execute before the condition and/or corresponding conditional branch have been evaluated and/or resolved, and thus the LOAD may speculatively reference an illegal address. Often, it is the case that “invalid” addresses (e.g., in particular the “null” page at linear address zero, etc.) are not given legal mappings by the operating system (e.g., the page is marked as “not present”, etc.), with the intent of exposing as page faults any “bad” pointer dereferencing or missing pointer validity checks by the software. In many conventional architectures (e.g., x86 or ARM), the hardware TLBs are not permitted to cache not-present entries; this typically manifests itself as an architectural rule that when an operating system changes a page mapping from invalid to valid, it need not invalidate the TLBs (e.g., which by decree do not hold invalid mappings, etc.).
However, when TLBs are not allowed to cache invalid entries, successive references to a “bad” address typically miss in the TLB, and generate separate requests (“page walk requests”), aimed at producing a valid mapping (yet ultimately fail to produce a valid TLB entry). These requests typically consume power, may introduce additional stalls into the system, and/or complicate fault handling. It may be desirable to “squash” these requests early, but traditional approaches directed at actually caching invalid mappings in the TLB (which might attempt to achieve an early “squash”) typically violate the architectural rule alluded to above.